Warp processor for dynamic translation of binaries to FPGA circuits

University of California System: University of California, Riverside
posted on 07/02/2009

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Traditional microprocessor software bits represent sequential instructions that are executed by a programmable microprocessor.   In contrast, modern FPGA software bits are mapped onto FPGA’s configurable logic fabric via a circuit.   Both software types free developers from needing to design hardware.  A computation may execute faster on an FPGA than as sequential instructions on a microprocessor because a circuit allows concurrency (single rather than multiple cycle passes) from the bit to the process level

UC’s invention has immense commercial applications as almost any kind of microprocessor-based technology can utilize the benefits of warp processing. These include everything from video and audio processing, encryption and decryption, encoding, compression and decompression and bioinformatics to mainframe computers and even relatively simple consumer electronic items such as TV’s.   Embedded systems such as medical instruments and security scanners can also perform real-time recognition using warp-enhanced FPGA’s.

1) The invention utilizes single pass optimizations that require less memory (up to 20 times less) and execution time than most current commercial approaches. 

2) The technique offers reduced energy consumption (up to 74%) over corresponding embedded benchmarks. 

3) Dynamic partitioning is completely transparent, allowing a designer to gain the benefits of partitioning, while writing a regular software application using standard software tools.

4) The warp processor’s dynamic partitioning can adapt to an application’s actual usage in real-time, eliminating the need for optimization via cumbersome static simulations.