Follow this innovation
[ via 
] [?]
Localized Silicon-On-Insulator (SOI) Wafer
University of California System: University of California, Santa Barbara
posted on 06/10/2009
A new and simple way to realize silicon-on-insulator (SOI) wafers with localized insulator region.
Suggested Uses
- Electronic and photonic devices
This technology is available for licensing.
Advantages
- 4.5X lower thermal impedance
- Improved thermal dissipation capacity of electronic and photonic devices
- Higher output power and reduced threshold currents
- Different devices can be integrated on the same substrate easily
Detailed Description
Researchers at the University of California, Santa Barbara have developed a new and simple way to realize silicon-on-insulator (SOI) wafers with localized insulator region. The fabrication is implemented by well-known CMOS technology and completely compatible to current SOI wafer manufacturing flow.
File Number: 18966
Other Information:
Background
Within the silicon-on-insulator (SOI) wafers the substrates are limited by thickness of the top device layer and BOX layer, plus potential surface morphology issue and material defects
| Copyright: | ©2009-2010, The Regents of the University of California |
|---|
This innovation currently is not available for online licensing. Please contact Franco Caporale at University of California System: University of California, Santa Barbara for more information.
request more info
ProfileFind more innovations
