Innovation
Exploiting Abundant Don't-Cares in Logic Synthesis
University of Michigan
posted on 08/27/2010
Exploiting Abundant Don't-Cares in Logic Synthesis
Innovation Details
Detailed Description
UM File # 3933
Background
To reduce circuit design complexity in the multibillion transistor era, System on Chip (SoC) and embedded systems heavily rely on reuse and third party IP components. Often, the design environment surrounding such components uses only a fraction of the functionality that these general-purpose components implement. The unused logic in those circuit blocks not only occupies valuable die area but also consumes more power, hurting the circuit's performance and quality. As a result, new synthesis optimization opportunities are available in simplifying these components to the subset of functionality required by the system in whicy they are embedded. Surprisingly, existing synthesis tools perform poorly in this context, which typically involves a small care set and a very large don't-care set.
Technology Description
Researchers at University of Michigan have developed a digital synthesis tool named Synthesis Within an Extensive Don't-care Environment (SWEDE), and synthesis techniques which can specialize a circuit using external don't-cares: FastShrink and CleanSlate. Unlike traditional synthesis tools that pursue maximal use of don't-cares by explicitly branching on different don't-care assignments, the greedy algorithms implicitly exploit the fact that most terms are don't-cares and quickly generate a small netlist. Further circuit optimization is performed, and this synthesis flow allows SWEDE to scale better when massive don't-cares exist. Empirical results show that SWEDE provides better synthesis quality than state-of-the-art tools while running 10X faster. In fact, SWEDE can handle designs as large as 30K cells with 0.5M care-set vectors in a few hours, demonstrating its superior scalability and efficiency.
Applications
• Acceleration of the most-frequent computation in a unit
• Synthesis for fast emulation
• Customization of third-party IP components in System on Chip designs
• Support for graceful wear-out of electronic devices
Advantages
• Consumes less power
• Produces small netlists in just a small fraction of the time
• Simple to use; only requires input vectors to the circuit that belong to the care terms
Background
To reduce circuit design complexity in the multibillion transistor era, System on Chip (SoC) and embedded systems heavily rely on reuse and third party IP components. Often, the design environment surrounding such components uses only a fraction of the functionality that these general-purpose components implement. The unused logic in those circuit blocks not only occupies valuable die area but also consumes more power, hurting the circuit's performance and quality. As a result, new synthesis optimization opportunities are available in simplifying these components to the subset of functionality required by the system in whicy they are embedded. Surprisingly, existing synthesis tools perform poorly in this context, which typically involves a small care set and a very large don't-care set.
Technology Description
Researchers at University of Michigan have developed a digital synthesis tool named Synthesis Within an Extensive Don't-care Environment (SWEDE), and synthesis techniques which can specialize a circuit using external don't-cares: FastShrink and CleanSlate. Unlike traditional synthesis tools that pursue maximal use of don't-cares by explicitly branching on different don't-care assignments, the greedy algorithms implicitly exploit the fact that most terms are don't-cares and quickly generate a small netlist. Further circuit optimization is performed, and this synthesis flow allows SWEDE to scale better when massive don't-cares exist. Empirical results show that SWEDE provides better synthesis quality than state-of-the-art tools while running 10X faster. In fact, SWEDE can handle designs as large as 30K cells with 0.5M care-set vectors in a few hours, demonstrating its superior scalability and efficiency.
Applications
• Acceleration of the most-frequent computation in a unit
• Synthesis for fast emulation
• Customization of third-party IP components in System on Chip designs
• Support for graceful wear-out of electronic devices
Advantages
• Consumes less power
• Produces small netlists in just a small fraction of the time
• Simple to use; only requires input vectors to the circuit that belong to the care terms
File Number: 3933
IP Protection
License Online
This innovation currently is not available for online licensing. Please contact Doug Hockstad at University of Michigan for more information.
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