The need for high-speed integrated circuits has led to widely using dynamic logic in the critical timing data-paths. CMOS Domino logic, a family of dynamic logic, offers speed and area advantages over conventional CMOS static logic. However, testing such circuits for manufacturing defects is difficult due to their design topologies. CMOS domino designs include footer and keeper transistors to counter problems like charge sharing and charge leakage. These transistors do not directly affect the logic behavior of the circuit. However, a large number of faults in those transistors are untestable using conventional tests based on purely logical fault models. A testable scheme is introduced that offers an efficient method of testing such faults. The feasibility of using this scheme to test CMOS domino circuits within larger systems like multiple bit adders is demonstrated.

File Number: 06UMR007  

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Case Manager: Keith D. Strassner, kdstrass@mst.edu